Semiconductor component having a stack of semiconductor chips and method for producing the same

ABSTRACT

A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another.

CROSS REFERENCE TO RELATED APPLICATION

This Utility patent application is a continuation application of U.S.application Ser. No. 10/598,143 filed Nov. 18, 2009, which claims thebenefit of the filing date of German Application No. DE 10 2004 008135.2, filed Feb. 18, 2004, and International Application No.PCT/DE2005/000215, filed Feb. 9, 2005, all of which are hereinincorporated by reference.

BACKGROUND

One embodiment of the invention relates to a semiconductor componenthaving a stack of semiconductor chips and a method for producing thesame, the semiconductor chips having contact areas which areelectrically connected via conductor portions in the semiconductor chipstack.

The increasing densification particularly in hardware for data storagearrangements and data processing requires semiconductor modules that areas compact as possible in conjunction with minimal space requirement.One possibility is afforded by the stacking of semiconductor chipsand/or semiconductor components to form a semiconductor module stack.However, there is an optimization problem in the fact that thecomponents of a stacked semiconductor module have to be wired among oneanother in space-saving fashion. The wiring solutions known to date workwith flip-chip contact connections and/or with bonding connections whichhave a considerable space requirement. Further connection techniquesprovide rewiring plates between the components to be stacked in order tosolve the wiring of a chip stack, with the result that the spacerequirement is likewise high. What is more, conventional solutionsimpose boundary condition and size condition on the components to bestacked, which impedes a freely selectable wiring and the stacking ofsemiconductor chips of arbitrary area sizes to form semiconductorcomponents. For these and other reasons, there is a need for the presentinvention.

SUMMARY

The invention provides a semiconductor component having a stack ofsemiconductor chips, the semiconductor chips having different sizes anda reliable, space-saving electrical connection between the stackedsemiconductor chips nevertheless being ensured.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a schematic cross section through a component havinga semiconductor chip stack of a first embodiment of the invention.

FIG. 2 illustrates a schematic plan view of a semiconductor componenthaving a semiconductor chip stack of a second embodiment of theinvention.

FIG. 3 illustrates a schematic cross section through four semiconductorchips stacked one on top of another for producing a semiconductorcomponent having a semiconductor chip stack of a third embodiment of theinvention.

FIG. 4 illustrates the schematic cross section of the semiconductor chipstack from FIG. 3 after encapsulation of the semiconductor chip stackwith a layer having nanoparticles.

FIG. 5 illustrates a side view of the semiconductor component of thethird embodiment of the invention after patterning of the layer havingnanoparticles that are illustrated in FIG. 4.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

One embodiment of the invention provides a semiconductor componenthaving a stack of semiconductor chips, the semiconductor chips of thesemiconductor chip stack being arranged in a manner fixed cohesively oneon top of another. For this purpose, the semiconductor chips havecontact areas extending as far as the edges of the semiconductor chips.In addition, conductor portions extend from at least one upper edge to alower edge of the edge sides of the semiconductor chips, and theyelectrically connect the contact areas of the semiconductor chips of thesemiconductor chip stack.

As a result of the cohesive connection between the semiconductor chipsand of the stack, the space requirement is minimized to the thickness ofthe semiconductor chips, especially as cohesive, areal connections ofthis type between the semiconductor chips take up only a fewmicrometers. The thickness of the semiconductor chip stack canfurthermore be reduced further by thinning the stacked semiconductorchips. By leading the contact areas on the active top side of thesemiconductor chips as far as the edges of the respective semiconductorchip, it is ensured that the conductor portions arranged on the edgesides can produce a reliable electrical contact between the contactareas of an upper semiconductor chip and the contact areas of asemiconductor chip arranged underneath. For this purpose, the twocontact areas to be connected do not have to be arranged directly oneabove the other, since the conductor portions on the edge sides of thesemiconductor chips also enable structures in which the contact areas ofan upper and of a lower semiconductor are arranged in a manner offsetwith respect to one another.

The conductor portions extending on the edge sides of the semiconductorchips do not limit the free selectability of the chip sizes that are tobe connected to one another. Thus, in one embodiment of the invention,the semiconductor chips may have different chip sizes. In that case, theconductor portions which connect two contact areas of two chips havingdifferent area sizes to one another may be led on edge regions of theactive top side of the semiconductor chips or on edge regions of therear sides of the semiconductor chips in such a way that virtually anydesired size differences may prevail between the semiconductor chips andare overcome by the line routing. A further advantage of this inventionis that alternately large-area and small-area semiconductor chips mayalso be stacked one above another since the conductor portions can beled in any desired manner along the edge sides, the top sides and therear sides of the semiconductor chips.

As a result of laying the contact areas to the edges of thesemiconductor chips, it is possible to effect a wiring of this type onthe edge sides of the semiconductor chips and thus on the edge sides ofthe semiconductor component in combination with wirings on non-coveredactive top sides and rear sides of the semiconductor chips. Theflexibility of this line routing which is restricted to the edge sidesof a semiconductor chip stack has the advantage over conventionalsolutions that the semiconductor chips can be adhesively bonded,soldered or diffusion-soldered one on top of another over the wholearea, without taking into consideration any flip-chip contacts orcontact pads or rewiring plates, in minimal space. As a result, stacksof semiconductor chips become possible in which crosstalk is minimizedand the feedback of signals via parasitic inductances remainssuppressed.

It is also possible for the semiconductor chips to have a differentnumber of contact areas at their edges. A wiring plan which takesaccount of this different number of contact areas is thencorrespondingly provided.

In contrast to bonding wires or flip-chip contacts, the electricallyconductive conductor portions are arranged adhesively on thesemiconductor chip edges, the semiconductor edge sides, thesemiconductor top sides and/or the semiconductor rear sides. The spacesaving is thus optimal since no bonding loops whatsoever or otherdistances as a result of flip-chip contacts, by way of example, enlargethe space requirement. Consequently, the semiconductor componentaccording to the invention having a stack of semiconductor chipsconstitutes an extremely high densification that has not been achievedheretofore, particularly in hardware for data storage arrangements anddata processing.

In order to achieve line routing of this type, the conductor portionshave an adherent plastic resist which is filled with metallicnanoparticles and is electrically conductive as soon as thenanoparticles have welded or fused together to form conductor portions.For this purpose, the nanoparticle-filled plastic resist is soluble in asolvent and can be stripped away from the side edges, the top sides, theedge sides and the rear sides of the semiconductor chips at thelocations at which conductor portions do not arise. In order to densifythe nanoparticles to form conductor portions, it is possible to uselaser writers which, by means of their laser beam, on the one handdensify and fuse together the nanoparticles and on the other handvaporize the plastic resist.

Patterning is also possible photolithographically if the plastic resisthas corresponding properties, but the interconnect with theplastic-embedded nanoparticles subsequently has to be separately treatedagain in order to fuse together the nanoparticles. Furthermore, insteadof individual, monolayer interconnect sections on the edge sides of thestack it is also possible to provide multilayer rewiring layers in whichnanoparticle-filled electrically conductive and patterned plastic resistlayers and insulation layers arranged in between alternate on the edgesides of the semiconductor chips. It is thus possible to accommodatecomplex circuit patterns on the edge sides of the semiconductor chipstack which cannot be realized by means of conventional bonding wiretechnology or by means of conventional flip-chip technology.

A method for producing a semiconductor component having a stack ofsemiconductor chips has the following process.

Firstly, semiconductor chips are produced with contact areas extendingas far as the edges of the respective semiconductor chip. Afterward, thesemiconductor chips are fixed cohesively one above another to form astack. This compact stack of semiconductor chips can then beencapsulated with a layer made of plastic resist which is filled withnanoparticles. Finally, this outer conductive encapsulation layer isthen patterned to form interconnect sections between the contact areasof semiconductor chips stacked one on top of another.

This method has the advantage that this enables the to date highestpossible densification, particularly in hardware for data storagedevices and data processing. In this case, it is particularlyadvantageous that the contact areas are no longer arranged in the edgeregion of a top side of a semiconductor chip, but rather extend as faras the edges of the semiconductor chip. Consequently, these edges of thecontact areas, after the cohesive fixing of the semiconductor chips oneabove another, can be short-circuited by the encapsulating conductivelayer firstly via the nanoparticles. This line can then be patterned,and all degrees of freedom of a three-dimensional wiring are availableto this patterning, so that the stack of semiconductor chips mayadvantageously have different semiconductor chip sizes and there is noneed to provide any size gradation of the kind that is a prerequisite inconventional technologies for stacking semiconductor chips in order towire the topmost semiconductor chip with the bottommost semiconductorchip of a stack.

The application of the layer made of nanoparticle-filled plastic resistto the semiconductor stack may be effected by means of a sprayingtechnique. Spraying techniques of this type provide for a relativelyuniform application of the nanoparticle-filled plastic resist, which isthen patterned to form conductor portions.

In a further preferred implementation of the method, the semiconductorstack, for encapsulation with a layer made of plastic resist, is dippedinto a bath of nanoparticle-filled plastic resist. The advantage of sucha dipping technique is that mass production and mass coating of thesemiconductor stack become possible, but the thicknesses achieved in theprocess are significantly higher than in the case of the sprayingtechnique.

For the patterning of the nanoparticle-filled plastic resist, a laserablation method is used which on the one hand vaporizes the plasticresist and on the other hand welds the nanoparticles together to forminterconnects. Where no laser removal of the plastic resist takes place,and thus where the nanoparticles are not welded together either, thenanoparticle-filled plastic resist can be stripped away or washed awayby means of corresponding solvents.

In principle, it is also possible to carry out the patterning of thenanoparticle-filled layer made of plastic resist to form interconnectsections by means of the photolithography methods. By way of example,projection photolithography may be successfully employed here on accountof the greatly patterned side edges of the semiconductor chips that arestacked one on top of another.

Finally, it is possible for the interconnect sections not to be attainedin the form of an encapsulation and subsequent pattern of a layer, butrather to apply them selectively by means of precision injectiontechniques from the outset. In the case of said precision injectiontechniques, a few micrometers fine steel of plastic resist which isfilled with nanoparticles is injected onto the edge sides of thesemiconductor chip stack. The interconnect sections are therebypractically drawn on the edge sides of the semiconductor stack.

If the connection density between the stacked semiconductor chips is tobe increased, then it is also possible to apply multilayer interconnectsections in alternation with insulation layers to the semiconductorstack either selectively or with the aid of the laser removal method orwith the aid of photolithography for processing. With this methodvariant, the number of conductor portions which connect the contactareas of the individual semiconductor chips on a semiconductor chipstack can advantageously be increased as desired.

To summarize, it can be stated that the invention makes it possible torealize production of stacked semiconductor chips with the smallestpossible spatial wiring and with geometry-independent chip sizes.Expensive rewiring plates between the stacked semiconductor chips arethereby avoided. Intermediate contact layers, such as flip-chip contactsor bonding wire connections, for example, also become superfluous withthe present invention. To that end, the contact areas of thesemiconductor chips are led outward as far as the semiconductor chipedges. This may be effected as early as at the front end or with a thinrewiring layer to be applied to the active top side of the semiconductorchips.

The semiconductor chips to be stacked are subsequently connectedcohesively to one another. This may be effected by means of an adhesivebonding process or a soldering process or a diffusion soldering process.This chip composite as a semiconductor chip stack is then dipped into asolution filled with electrically conductive metallic or metallicallycoated nanoparticles or, as an alternative, said solution is sprayedonto the stack of semiconductor chips. Afterward, the particles can bepatterned by means of laser bombardment and fused together to forminterconnects. The excess particle solution that was not combined intointerconnects is then removed either by being washed away or by beingdipped into a suitable solvent.

Moreover, in this way multilayer rewiring structures can be produced andcan be applied by additional process by introduction of correspondinginsulation layers made of a dielectric. Required plated-through holes tothe active top sides of the semiconductor chips can likewise beuncovered by means of laser removal and a conductive connection cansubsequently be applied and patterned once again by means of ananoparticle solution. To conclude the process, the semiconductor chipstack may also be applied to a base chip or to a corresponding carrieror be provided with external contacts on its exterior sides.

If a protective plastic cap is to be provided for the protection of thesemiconductor chip stack and the contact areas, and also the rewiringhaving nanoparticles, it is possible to provide less expensive andhigher-viscosity molding compositions than hitherto in the moldingprocess, especially as the semiconductor chip stack forms a stable andcompact semiconductor body. With this type of stacking, all wireconnections are obviated. In particular, very thin housings can berealized reliably since the space requirement for wires, for bumpcontacts or for flip-chip contacts is obviated.

FIG. 1 illustrates a schematic cross section through a semiconductorcomponent 14 having a semiconductor chip stack (100) of a firstembodiment of the invention. The semiconductor chip stack 100 has alower semiconductor chip 1 and an upper semiconductor chip 2 stackedthereon. The semiconductor chips 1, 2 have top sides 11, rear sides 12and edge sides 10. In this first embodiment of the invention, the topside 11 of the lower semiconductor chip 1, which carries the activesemiconductor elements of an integrated circuit, is cohesively connectedto the rear side 12 of the upper semiconductor chip 2. The top sides 11of the semiconductor chips 1 and 2 have contact areas 5 extending as faras the edges 6 of the top sides 11 of the semiconductor chips 1 and 2.Said edges which here have the contact areas 5 are called upper edges 8hereinafter, and the edges that form between the edge sides 10 and therear side 12 of the semiconductor chips 1 and 2 are identified as loweredges 9 hereinafter. The stack 100 of semiconductor chips 1 and 2 iscovered by an insulation layer 16 on its surfaces and has windows 18 inthe region of the contact areas 5, both on the edge sides 10 and on thetop sides 11, so that it is possible to access said contact areas at theedges 6.

On said insulation layer 16 with windows 18 to the contact areas 5,there is applied a patterned layer 15 made of nanoparticle-filledplastic resist, which, in this embodiment of the invention, has contactwindows 19 to the underside of the semiconductor stack 100, via whichwindows it is possible to access the electrically conductive layer 15made of nanoparticle-filled plastic resist. A further insulation layer17 is applied on the patterned conductive layer 15. On said secondinsulation layer 17, it is possible, if necessary, to apply furtherconductive layers 15 made of nanoparticle-filled plastic resist inalternation with insulation layers 16, 17 and it is thus possible tocoat the edge sides 10, the top sides 11 and the rear sides 12 of thesemiconductor chip 1 or 2 of the semiconductor chip stack 100 with amultilayer rewiring structure 23.

The electrically conductive layer 15 is patterned in such a way thatconductor portions 7 are formed which, by way of example, as isillustrated in FIG. 1, can connect an external contact area 20 on theunderside of the semiconductor chip stack 100 via the edge sides 10 andalso the top sides 11 to the contact areas 5 on the first and secondsemiconductor chips. Said conductor portions arise as a result of ananoparticle-filled plastic resist being applied to the first insulationlayer 16 and being heated by means of laser removal, the resistcomponent volatilizing, while the nanoparticles are densified to formconductor portions 7.

Conductor portions 7 of this type may extend from the underside of thesemiconductor chip stack 100 as far as the top side 11 of thesemiconductor chip stack 100 and in the process connect the contactareas 5 of both semiconductor chips 1, 2 to one another withoutrequiring through-etchings through the semiconductor chips. Thoseregions of the nanoparticle-filled plastic resist which are notpatterned to form conductor portions 7 can be dissolved in a solventbath and removed. The laser removal makes it possible to realizecorresponding conductor portions 7 both on the underside of thesemiconductor chip stack 100 and on the top sides 11 of thesemiconductor chips 1 and 2 of the semiconductor chip stack 100, and onthe edge sides 10.

In this embodiment, the contact windows 19, on the underside of thesemiconductor chip stack 100, are covered with an external contact area20, which can carry an external contact 21, illustrated by dashed lineshere. For illustrating the invention, the dimensions are not true toscale, so it is possible, by way of example, for the coating of the rearsides 12, edge sides 10 and top sides 11 of the semiconductor chip stack100 by a system having an insulation layer 16, a conduction layer 15 anda further insulation layer 17 to have a thickness d of only a fewmicrometers.

The semiconductor chips have a thickness D that may be between 50 μm and700 μm. The cohesive connecting layer 22 may have an adhesive or asoldering material having a thickness w likewise of only a fewmicrometers. Compared with these thickness dimensions, the areadimensions of the semiconductor chips are significantly larger and mayhave dimensions in the centimeters range. By contrast, the contact areas5 on the active top sides 11 of the semiconductor chips 1 and 2 arelikewise only several tens of μm in size and, on account of theconductor portions 7 made of nano-filled plastic resist according to theinvention, can furthermore be reduced in size to a few micrometerssquared, whereby it is possible to achieve a high density in conjunctionwith a small pitch or small step size between the contact areas 5.

FIG. 2 illustrates a schematic plan view of a semiconductor component 24having a semiconductor chip stack 200 of a second embodiment of theinvention. This plan view illustrates three semiconductor chips 1, 2 and3 stacked one on top of another. In this case, the size of the top sides11 of the semiconductor chips 1 to 3 decreases from 1 to 3, so that thetopmost semiconductor chip 3 has the smallest area and the bottommostsemiconductor chip 1 has the largest area. This downwardly increasingsize of the semiconductor chips 1 to 3 was chosen in this embodiment inorder to illustrate the rewiring structure 23 of such a semiconductorchip stack 200 with the aid of the plan view. In this case, theconductor portions 7 run partly on the top sides 11 of the semiconductorchips and partly on the edge sides 10 of the semiconductor chips.

The contact areas 5 once again reach as far as the edges 6 in each ofthe semiconductor chips 1 to 3, whereby a three-dimensional wiringbecomes possible. The decrease in the size of the top sides 11 of thesemiconductor chips 1 to 3 from the bottommost semiconductor chip 1 tothe topmost semiconductor chip 3 is not absolutely necessary in the caseof the rewiring structure 23 according to the invention since the rearsides—as already illustrated in FIG. 1 with the rear side 12 of thesemiconductor chip 1—of the semiconductor chips can also be providedwith conductor portions 7 with the aid of the laser removal method, byway of example. This means that the semiconductor chips 1 to 3 may have,in principle, any desired size in the stacking order in this new wiringtechnique, as is illustrated in the subsequent figures.

FIGS. 3 to 5 illustrate stages in the production of a semiconductorcomponent having a semiconductor chip stack of a third embodiment of theinvention.

FIG. 3 illustrates in this respect a schematic cross section throughfour semiconductor chips 1 to 4 stacked one on top of another forproducing a semiconductor component 34 having a semiconductor stack 300of this third embodiment of the invention. Of the four semiconductorchips 1 to 4 stacked one on top of another, the bottommost semiconductorchip 1 has the largest active top side 11. The semiconductor chip 2stacked by its rear side 12 on the semiconductor chip 1 has a smalleractive top side 11 by comparison therewith, so that the thirdsemiconductor chip 3 projects beyond the edge sides 10 of the secondsemiconductor chip 2. A semiconductor chip 4 having a smaller active topside 11 is in turn arranged on the third semiconductor chip 3.

The semiconductor chips 1, 2, 3 and 4 are cohesively connected by meansof an adhesive via the connecting layers 22. While the contact areas 5of the active top sides 11 of the semiconductor chips 1, 3 and 4 arefreely accessible, the top side 11 of the contact areas 5 of thesemiconductor chip 2 is covered, but on account of the contact areas 5being led, according to the invention, to the edge sides 10 of thesemiconductor chip 2, contact can be made with the edge sides 10 of thecontact areas 5 of the semiconductor chip 2 as well.

A semiconductor chip stack 300 prepared in this way can then be coveredwith an electrically conductive layer.

FIG. 4 illustrates a schematic cross section of a semiconductor chipstack 300 illustrated in FIG. 3 after encapsulation of the semiconductorchip stack 300 with a layer 15 having nanoparticles. Said layer 15having nanoparticles is sprayed onto all the exterior sides of thesemiconductor chip stack 300 by a plastic resist which is filled withelectrically conductive nanoparticles being sprayed on or by thesemiconductor chip stack being dipped into a bath containing a plasticresist having filled nanoparticles. After drying of the resist withprecuring of the resist, said layer 15 having nanoparticles can then bepatterned.

FIG. 5 illustrates a side view of the semiconductor component 34 afterpatterning of the layer 15 having nanoparticles in accordance with FIG.4. The patterning of the semiconductor chip stack 300 to form asemiconductor component 34 was achieved in the third embodiment of theinvention by guiding a laser beam along the tracks that are marked blackin FIG. 5. In the process, the nanoparticles are contacted with oneanother through to welding, while the plastic resist simultaneouslyevaporates. Interconnects 25 to 33 arise in the process, as illustratedin the side view of FIG. 5, which interconnects, with differentinterconnect routing, interconnect or connect the different contactareas 5 of the semiconductor chips 1 to 4 to one another. The contactareas 5 of the second semiconductor chip 2 of the semiconductor chipstack 300 are contact-connected on their edge sides 10 during thepatterning, especially as the semiconductor chip 2, as is illustrated inFIG. 4, is smaller than the semiconductor chip 3 arranged above it. Therewiring technique according to the invention is thus able also tocreate electrical connections to contact areas 5 which have only theircross section available for the electrical connection to an interconnect7. The interconnects 7 on the rear side 12 of the semiconductor chip 3are realized by means of a deflection optic for a laser during thisstacking of the semiconductor chips 1 to 4.

With this technique it is possible to realize a wide variety ofstructures, as is illustrated with the various interconnects 25 to 33illustrated here. Thus, the interconnects can branch, as is illustratedwith the interconnects 25, 26 and 27, or they are led together, asillustrated by the interconnects 28, 30 and 31. Alternatively, theymerely serve to produce a connection between a plurality ofsemiconductor chips 1 to 4, as is illustrated for example by theinterconnects 29, 32 and 33 in this side view. Such a simple wiringpattern which can be produced by means of relatively inexpensivefabrication methods is only possible by virtue of the fact that firstlya plastic resist having nanoparticles is used and secondly the contactareas of the individual semiconductor chips 1 to 4 are led as far as theedges of the respective semiconductor chip 1 to 4.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A semiconductor component comprising: a stack ofsemiconductor chips, the semiconductor chips being arranged in a mannerfixed cohesively one on top of another, the semiconductor chips eachcomprising a top side and a rear side with edge sides extending therebetween and having contact areas extending as far as the edge sides ofthe semiconductor chips, the contact areas having regions accessiblefrom both the top side and the edge sides of the semiconductor chips;and conductor portions extending from at least one upper edge to a loweredge of the edge sides of the semiconductor chips and electricallyconnecting the contact areas of the semiconductor chips of thesemiconductor chip stack via at least the regions of the contact areasaccessible from the edge sides of the semiconductor chips.
 2. Thesemiconductor component as claimed in claim 1, comprising thesemiconductor chips having two or more different chip sizes.
 3. Thesemiconductor component as claimed in claim 1, comprising thesemiconductor chips having a different number of contact areas at theiredges.
 4. The semiconductor component as claimed in claim 1, wherein thecontact areas are arranged on one or more of the semiconductor edgesides, the semiconductor top side, and the semiconductor rear side so asto enable a freely selectable stacking order for the semiconductor chipsforming the stack.
 5. The semiconductor component as claimed in claim 1,comprising where the conductor portions comprise an adherent plasticresist which is filled with metallic nanoparticles and is electricallyconductive.
 6. The semiconductor component as claimed in claim 5,comprising were the nanoparticle-filled plastic resist is soluble in asolvent.
 7. The semiconductor component as claimed in claim 1,comprising where the nanoparticle-filled plastic resist is patterned bylaser removal.
 8. The semiconductor component as claimed in claim 1,comprising where the nanoparticle-filled plastic resist is patternedphotolithographically.
 9. The semiconductor component as claimed inclaim 1, comprising where the semiconductor chip stack comprises amultilayer rewiring layer comprising nanoparticle-filled electricallyconductive patterned plastic resist layers and insulation layersarranged in between on the edge sides of the semiconductor chips.
 10. Asemiconductor component comprising: a stack of semiconductor chips, thesemiconductor chips being arranged in a manner fixed cohesively one ontop of another, the semiconductor chips comprising contact areasextending as far as the edges of the semiconductor chips; conductorportions extending from at least one upper edge to a lower edge of theedge sides of the semiconductor chips and electrically connecting thecontact areas of the semiconductor chips of the semiconductor chipstack; where the electrically conductive conductor portions are arrangedadhesively on the semiconductor chip edges, the semiconductor edgesides, the semiconductor top side and/or the semiconductor rear sidewith a freely selectable stacking order; and where the conductorportions comprise an adherent plastic resist which is filled withmetallic nanoparticles and is electrically conductive.
 11. Thesemiconductor component as claimed in claim 10, comprising were thenanoparticle-filled plastic resist is soluble in a solvent.
 12. Thesemiconductor component as claimed in claim 10, comprising where thenanoparticle-filled plastic resist is patterned by laser removal. 13.The semiconductor component as claimed in claim 10, comprising where thenanoparticle-filled plastic resist is patterned photolithographically.14. The semiconductor component as claimed in claim 10, comprising wherethe semiconductor chip stack comprises a multilayer rewiring layercomprising nanoparticle-filled electrically conductive patterned plasticresist layers and insulation layers arranged in between on the edgesides of the semiconductor chips.
 15. The semiconductor component asclaimed in claim 14, comprising the semiconductor chips having two ormore different chip sizes; and having a different number of contactareas at their edges.
 16. A semiconductor component comprising: a stackof semiconductor chips, the semiconductor chips being arranged in amanner fixed cohesively one on top of another, the semiconductor chipscomprising contact areas extending as far as the edges of thesemiconductor chips; and means for providing conductor portionsextending from at least one upper edge to a lower edge of the edge sidesof the semiconductor chips and electrically connecting the contact areasof the semiconductor chips of the semiconductor chip stack.